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In this talk, we'll dive into the world of reconfigurable architectures, starting with the fundamental principles of Field-Programmable Gate Arrays (FPGAs). We'll explore their internal structure, from configurable logic blocks to programmable interconnects, and the core concepts that enable them to be reprogrammed to perform a vast range of digital tasks.  We will then introduce the OpenFPGA project, an open-source framework that democratizes the design of custom, domain-specific FPGAs, moving beyond the traditional fixed architectures. Finally, we'll shift our focus to the future, examining how emerging device technologies that inherently possess reconfigurability at the hardware level could reshape our design methodologies and necessitate new abstraction models to fully harness their potential. This presentation aims to provide a comprehensive view, from foundational knowledge to the cutting-edge of reconfigurable computing.

This talk introduces the Emerald system, a new technology that uses wireless sensing and machine learning to implement touchless health monitoring. An Emerald device in the home transmits low-power radio signals and records their reflections. The recorded data is then passed to the cloud for further processing using neural network algorithms. The monitoring system can infer the movements, breathing, heart rates, and sleep stages of people in their homes, without requiring them to wear any sensors. By monitoring physiological signals continuously over a period of months, the system can automatically detect changes in health conditions. The talk will describe the underlying technology and present examples of its application in clinical drug trials.

There are a number of factors that constrain computing hardware that it seems people often forget: from the magic (no static power) and cost (min. operating voltages) of CMOS gates to the fact that building domain specific hardware doesn’t automatically improve the application efficiency. Both performance and energy efficiency depend on exploiting locality, parallelism, operation specialization (listed in order of importance) and this holds for your logic gates and overall system. If your application/algorithm doesn’t have these characteristics, domain specific hardware won’t help. In fact, in all cases that I know about, to achieve the desired performance/energy efficiency gains requires changing the applications to provide more locality and parallelism to exploit. This talk will review some of the fundamental constraints on hardware design (in any technology) that I have learned, from dealing with devices that use electric field to control current flow, to building large machine learning accelerators. Since cost is a constraint is almost all systems, I will also talk about costs, and how it affects the type of hardware you design.

Computing is bottlenecked by data. Large amounts of application data overwhelm the storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications' performance, efficiency, and scalability are bottlenecked by data movement. In this talk, we describe three major shortcomings of modern computers in terms of 1) dealing with data, 2) taking advantage of vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent computing architecture should be designed to handle data well. We posit that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give examples of how to exploit these principles to design a much more efficient and higher performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising directions: 1) processing using memory, which exploits the fundamental operational properties of memory chips to perform massively-parallel computation in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory chips, the logic layer of 3D-stacked technologies, or memory controllers to enable near-memory computation with high memory bandwidth and low memory latency. We show both types of architectures can enable order(s) of magnitude improvements in performance and energy consumption of many important workloads, such as artificial intelligence, machine learning, graph analytics, database systems, video processing, climate modeling, genome analysis. We discuss how to enable adoption of such fundamentally more intelligent architectures, which are key to efficiency, performance, and sustainability. We conclude with some research opportunities in and guiding principles for future computing architecture and system designs. An accompanying overview of modern memory-centric computing ideas & systems can be found at https://arxiv.org/pdf/2012.03112 ("A Modern Primer on Processing in Memory", updated February 2025). A shorter invited paper from IMW 2025 is at https://arxiv.org/pdf/2505.00458 (“Memory-Centric Computing: Solving Computing’s Memory Problem”, May 2025)