Abstract
Quantum hardware is rapidly approaching the fault tolerant regime. This brings the potential to run quantum circuits with failure rates that are significantly below what is possible with ‘bare’ quantum hardware, opening a whole realm of possibilities for new quantum algorithms of both increasing breadth and depth. The challenge for the QEC theorist is to develop strategies to perform fault tolerant operations efficiently, minimizing overheads, within the constraints of particular quantum hardware, and adapted to the relevant error mechanisms.
I’ll present an overview of QEC and fault tolerance from the perspective of a theorist, with an emphasis on what I see as the open challenges for the field over the next few years. I will also present some of our recent work at Sydney on resource-efficient approaches for fault tolerance.\